1. Technical Field
The present invention relates to a signal generating apparatus and a test apparatus.
2. Related Art
Japanese Patent Application Publication No. 2006-41640 discloses a PLL circuit that adds voltage to a control voltage supplied to a VCO, according to jitter. This PLL circuit can generate a clock signal into which jitter is injected.
However, only a low-frequency voltage is supplied to the VCO, and so this PLL circuit cannot inject high-frequency jitter. Accordingly, the PLL circuit cannot apply jitter with a frequency higher than the loop band, for example.
By providing a jitter injection circuit at a stage after the PLL circuit, jitter with a frequency higher than the loop band of the PLL circuit can be injected into the clock signal. However, when providing the jitter injection circuit at a stage after the PLL circuit, propagation delay characteristics of the jitter injection circuit itself become a problem.
For example, in a jitter tolerance test for a communication interface or the like, operation of a device under test is tested by supplying the device under test with a test signal into which jitter is injected. In such a test, the test signal is supplied to the device under test at precise timings, and so it is desirable that the propagation delay characteristics of the clock generating circuit remain constant regardless of the frequency of the clock signal.